/**
 * \file adrv9009/profiles/tx_bw100_ir122p88_rx_bw100_or122p88_orx_bw100_or122p88_dc122p88/talise_config.c
 * \brief Contains Talise configuration settings for the Talise API
 *
 * Copyright 2015-2017 Analog Devices Inc.
 * Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
 *
 * The top level structure taliseDevice_t talDevice uses keyword
 * extern to allow the application layer main() to have visibility
 * to these settings.
 *
 * This file may not be fully complete for the end user application and
 * may need to updated for AGC, GPIO, and DAC full scale settings.
 * To create a full initialisation routine, the user should also refer to the
 * Iron Python initialisation routine generated by the GUI, and also the Talise User Guide.
 *
 */

 #include "talise_types.h"
 #include "talise_config.h"
 #include "talise_error.h"
 #include "talise_agc.h"
 #include "app_config.h"
 
 int16_t txFirCoefs[20] = {33,-77,123,-158,171,-112,-155,1040,-3011,20121,-3011,1040,-155,-122,171,-158,123,-77,33,0};
 
 int16_t rxFirCoefs[48] = {-7,-23,33,50,-70,-110,144,205,-259,-356,437,581,-698,-916,1082,1415,-1655,-2209,2567,3615,-4351,-7169,9329,31129,31129,9329,-7169,-4351,3615,2567,-2209,-1655,1415,1082,-916,-698,581,437,-356,-259,205,144,-110,-70,50,33,-23,-7};
 
 int16_t obsrxFirCoefs[48] = {-7,-21,31,48,-67,-106,124,164,-275,-334,440,552,-694,-872,1069,1351,-1633,-2111,2541,3477,-4295,-6877,9433,30825,30825,9433,-6877,-4295,3477,2541,-2111,-1633,1351,1069,-872,-694,552,440,-334,-275,164,124,-106,-67,48,31,-21,-7};
 
 /**
  *  TalDevice a structure used by the Talise API to hold the platform hardware
  *  structure information, as well as an internal Talise API state container
  *  (devStateInfo) of runtime information used by the API.
  **/
 taliseDevice_t talDevice = {
	 .devHalInfo = NULL,     /* < Insert Customer Platform HAL State Container here>*/
	 /* devStateInfo is maintained internal to the Talise API, just create the memory */
	 .devStateInfo = {0}
 };
 
 taliseInit_t talInit = {
	 /* SPI settings */
	 .spiSettings =
	 {
		 .MSBFirst            = 1,  /* 1 = MSBFirst, 0 = LSBFirst */
		 .enSpiStreaming      = 0,  /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
		 .autoIncAddrUp       = 1,  /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
		 .fourWireMode        = 1,  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
		 .cmosPadDrvStrength  = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */
	 },
 
	 /* Rx settings */
	 .rx =
	 {
		 .rxProfile =
		 {
			 .rxFir =
			 {
				 .gain_dB = -6,                /* filter gain */
				 .numFirCoefs = 48,            /* number of coefficients in the FIR filter */
				 .coefs = &rxFirCoefs[0]
			 },
			 .rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
			 .rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
			 .rhb1Decimation = 1,            /* RX Half band 1 decimation (1 or 2) */
			 .rxOutputRate_kHz = 245760,            /* Rx IQ data rate in kHz */
			 .rfBandwidth_Hz = 200000000,    /* The Rx RF passband bandwidth for the profile */
			 .rxBbf3dBCorner_kHz = 200000,    /* Rx BBF 3dB corner in kHz */
			 .rxAdcProfile = {185, 141, 172, 90, 1280, 942, 1332, 90, 1368, 46, 1016, 19, 48, 48, 37, 208, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},            /* pointer to custom ADC profile */
			 .rxDdcMode = TAL_RXDDC_BYPASS,   /* Rx DDC mode */
			 .rxNcoShifterCfg =
			 {
				 .bandAInputBandWidth_kHz = 0,
				 .bandAInputCenterFreq_kHz = 0,
				 .bandANco1Freq_kHz = 0,
				 .bandANco2Freq_kHz = 0,
				 .bandBInputBandWidth_kHz = 0,
				 .bandBInputCenterFreq_kHz = 0,
				 .bandBNco1Freq_kHz = 0,
				 .bandBNco2Freq_kHz = 0
			 }
		 },
		 .framerSel = TAL_FRAMER_A,            /* Rx JESD204b framer configuration */
		 .rxGainCtrl =
		 {
			 .gainMode = TAL_MGC,            /* taliserxGainMode_t gainMode */
			 .rx1GainIndex = 255,            /* uint8_t rx1GainIndex */
			 .rx2GainIndex = 255,            /* uint8_t rx2GainIndex */
			 .rx1MaxGainIndex = 255,            /* uint8_t rx1MaxGainIndex */
			 .rx1MinGainIndex = 195,            /* uint8_t rx1MinGainIndex */
			 .rx2MaxGainIndex = 255,            /* uint8_t rx2MaxGainIndex */
			 .rx2MinGainIndex = 195            /* uint8_t rx2MinGainIndex */
		 },
		 .rxChannels = TAL_RX1RX2,                /* The desired Rx Channels to enable during initialization */
	 },
 
 
	 /* Tx settings */
	 .tx =
	 {
		 .txProfile =
		 {
			 .dacDiv = 1,                        /* The divider used to generate the DAC clock */
			 .txFir =
			 {
				 .gain_dB = 6,                        /* filter gain */
				 .numFirCoefs = 20,                    /* number of coefficients in the FIR filter */
				 .coefs = &txFirCoefs[0]
			 },
			 .txFirInterpolation = 1,                    /* The Tx digital FIR filter interpolation (1,2,4) */
			 .thb1Interpolation = 2,                    /* Tx Halfband1 filter interpolation (1,2) */
			 .thb2Interpolation = 2,                    /* Tx Halfband2 filter interpolation (1,2)*/
			 .thb3Interpolation = 2,                    /* Tx Halfband3 filter interpolation (1,2)*/
			 .txInt5Interpolation = 1,                    /* Tx Int5 filter interpolation (1,5) */
			 .txInputRate_kHz = 245760,                    /* Primary Signal BW */
			 .primarySigBandwidth_Hz = 75000000,    /* The Rx RF passband bandwidth for the profile */
			 .rfBandwidth_Hz = 200000000,            /* The Tx RF passband bandwidth for the profile */
			 .txDac3dBCorner_kHz = 200000,                /* The DAC filter 3dB corner in kHz */
			 .txBbf3dBCorner_kHz = 100000,                /* The BBF 3dB corner in kHz */
			 .loopBackAdcProfile = {243, 143, 181, 90, 1280, 485, 1275, 37, 1317, 23, 797, 35, 48, 48, 30, 174, 0, 0, 0, 0, 44, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}
		 },
		 .deframerSel = TAL_DEFRAMER_A,                    /* Talise JESD204b deframer config for the Tx data path */
		 .txChannels = TAL_TX1TX2,                            /* The desired Tx channels to enable during initialization */
		 .txAttenStepSize = TAL_TXATTEN_0P05_DB,            /* Tx Attenuation step size */
		 .tx1Atten_mdB = 0,                            /* Initial Tx1 Attenuation */
		 .tx2Atten_mdB = 0,                            /* Initial Tx2 Attenuation */
		 .disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO    /* Options to disable the transmit data when the RFPLL unlocks. */
	 },
 
 
	 /* ObsRx settings */
	 .obsRx =
	 {
		 .orxProfile =
		 {
			 .rxFir =
			 {
				 .gain_dB = 6,                /* filter gain */
				 .numFirCoefs = 48,            /* number of coefficients in the FIR filter */
				 .coefs = &obsrxFirCoefs[0]
			 },
			 .rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
			 .rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
			 .rhb1Decimation = 1,            /* RX Half band 1 decimation (1 or 2) */
			 .orxOutputRate_kHz = 245760,            /* Rx IQ data rate in kHz */
			 .rfBandwidth_Hz = 200000000,    /* The Rx RF passband bandwidth for the profile */
			 .rxBbf3dBCorner_kHz = 225000,    /* Rx BBF 3dB corner in kHz */
			 .orxLowPassAdcProfile = {185, 141, 172, 90, 1280, 942, 1332, 90, 1368, 46, 1016, 19, 48, 48, 37, 208, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
			 .orxBandPassAdcProfile = {185, 141, 172, 90, 1280, 942, 1332, 90, 1368, 46, 1016, 19, 48, 48, 37, 208, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
			 .orxDdcMode = TAL_ORXDDC_DISABLED,   /* ORx DDC mode */
			 .orxMergeFilter  = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
		 },
		 .orxGainCtrl =
		 {
			 .gainMode = TAL_MGC,
			 .orx1GainIndex = 255,
			 .orx2GainIndex = 255,
			 .orx1MaxGainIndex = 255,
			 .orx1MinGainIndex = 195,
			 .orx2MaxGainIndex = 255,
			 .orx2MinGainIndex = 195
		 },
		 .framerSel = TAL_FRAMER_B,                /* ObsRx JESD204b framer configuration */
		 .obsRxChannelsEnable = TAL_ORX1ORX2,        /* The desired ObsRx Channels to enable during initialization */
		 .obsRxLoSource = TAL_OBSLO_RF_PLL                /* The ORx mixers can use the TX_PLL */
	 },
 
	 /* Digital Clock Settings */
	 .clocks =
	 {
		 .deviceClock_kHz = 122880,            	/* CLKPLL and device reference clock frequency in kHz */
		 .clkPllVcoFreq_kHz = 9830400,        	/* CLKPLL VCO frequency in kHz */
		 .clkPllHsDiv = TAL_HSDIV_2P5,           /* CLKPLL high speed clock divider */
		 .rfPllUseExternalLo = 0,                /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
		 .rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC                /* RFPLL MCS (Phase sync) mode */
	 },
 
	 /* JESD204B settings */
	 .jesd204Settings =
	 {
		 /* Framer A settings */
		 .framerA =
		 {
			 .bankId = 1,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
			 .deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
			 .lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
			 .M = 4,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
			 .K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
			 .F = 4,                            /* F (number of bytes per frame) */
			 .Np = 16,                            /* Np (converter sample resolution) */
			 .scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
			 .externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
			 .serializerLanesEnabled = 0x03,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
			 .serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
			 .lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
			 .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			 .syncbInSelect = 0,                /* syncbInSelect; */
			 .overSample = 0,                    /* 1=overSample, 0=bitRepeat */
			 .syncbInLvdsMode = 1,
			 .syncbInLvdsPnInvert = 0,
			 .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		 },
		 /* Framer B settings */
		 .framerB =
		 {
			 .bankId = 0,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
			 .deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
			 .lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
			 .M = 2,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
			 .K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
			 .F = 2,                            /* F (number of bytes per frame) */
			 .Np = 16,                            /* Np (converter sample resolution) */
			 .scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
			 .externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
			 .serializerLanesEnabled = 0x0C,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
			 .serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
			 .lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
			 .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			 .syncbInSelect = 1,                /* syncbInSelect; */
			 .overSample = 0,                    /* 1=overSample, 0=bitRepeat */
			 .syncbInLvdsMode = 1,
			 .syncbInLvdsPnInvert = 0,
			 .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		 },
		 /* Deframer A settings */
		 .deframerA =
		 {
			 .bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
			 .deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
			 .lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
			 .M = 4,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
			 .K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
			 .scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
			 .externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
			 .deserializerLanesEnabled = 0x0F,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
			 .deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
			 .lmfcOffset = 17,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
			 .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			 .syncbOutSelect = 0,                /* SYNCBOUT0/1 select */
			 .Np = 16,                /* Np (converter sample resolution) */
			 .syncbOutLvdsMode = 1,
			 .syncbOutLvdsPnInvert = 0,
			 .syncbOutCmosSlewRate = 0,
			 .syncbOutCmosDriveLevel = 0,
			 .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		 },
		 /* Deframer B settings */
		 .deframerB =
		 {
			 .bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
			 .deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
			 .lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
			 .M = 0,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
			 .K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
			 .scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
			 .externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
			 .deserializerLanesEnabled = 0x00,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
			 .deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
			 .lmfcOffset = 0,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
			 .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			 .syncbOutSelect = 1,                /* SYNCBOUT0/1 select */
			 .Np = 16,                /* Np (converter sample resolution) */
			 .syncbOutLvdsMode = 1,
			 .syncbOutLvdsPnInvert = 0,
			 .syncbOutCmosSlewRate = 0,
			 .syncbOutCmosDriveLevel = 0,
			 .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		 },
		 .serAmplitude = 15,                    /* Serializer amplitude setting. Default = 15. Range is 0..15 */
		 .serPreEmphasis = 1,                /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */
		 .serInvertLanePolarity = 0,            /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
		 .desInvertLanePolarity = 0,            /* Deserializer Lane PN inversion select.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */
		 .desEqSetting = 1,                    /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */
		 .sysrefLvdsMode = 1,                /* Use LVDS inputs on Talise for SYSREF */
		 .sysrefLvdsPnInvert = 0              /*0= Do not PN invert SYSREF */
	 }
 };
 
 //Only needs to be called if user wants to setup AGC parameters

 //Only needs to be called if user wants to setup AGC parameters
 taliseAgcCfg_t rxAgcCtrl = {
	4,			// agcPeakWaitTime
	255,		// agcRx1MaxGainIndex
	195,		// agcRx1MinGainIndex
	255,		// agcRx2MaxGainIndex
	195,		// agcRx2MinGainIndex
	150,		/* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */
	10,		// agcRx1AttackDelay
	10,		// agcRx2AttackDelay
	16,		// agcSlowLoopSettlingDelay
	0,			// agcLowThreshPreventGain
	1,			// agcChangeGainIfThreshHigh
	0,			// agcPeakThreshGainControlMode
	0,			// agcResetOnRxon
	0,			// agcEnableSyncPulseForGainCounter
	1,			// agcEnableIp3OptimizationThresh
	31,		// ip3OverRangeThresh
	246,		// ip3OverRangeThreshIndex
	4,			// ip3PeakExceededCnt
	1,          /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
	/* agcPower */
	{
		1,			// powerEnableMeasurement [1: power measurement block enabled]
		1,			// Uses RFIR output for power measurement.  
		0,			// Uses DC offset block output for power measurement.
		42,			// underRangeHighPowerThresh [Threshold in dBFS (negative value assumed), which defines the lower boundary on the stable region 0-127] 
		2,			// underRangeLowPowerThresh [Offset (negative value assumed) from underRangeHighPowerThresh, which defines the outer boundary of the power based AGC convergence.]
		1,			// underRangeHighPowerGainStepRecovery
		1,			// underRangeLowPowerGainStepRecovery
		5,			// powerMeasurementDuration
		5,			// rx1TddPowerMeasDuration
		1,			// rx1TddPowerMeasDelay
		5,			// rx2TddPowerMeasDuration
		1,			// rx2TddPowerMeasDelay
		40,			// upper0PowerThresh [Threshold in dBFS (negative value assumed), which defines the upper boundary on the stable region (no gain change based on power measurement) of the power detect gain control mode. ]
		2,			// upper1PowerThresh [Offset (positive value assumed) from upper0PowerThresh, which defines the outer boundary of the power based AGC convergence. ]
		0,			// powerLogShift
		1,			// overRangeLowPowerGainStepAttack
		1,			// overRangeHighPowerGainStepAttack
	},
	/* agcPeak */
	{
		205,		// agcUnderRangeLowInterval_ns
		2,			// agcUnderRangeMidInterval
		4,			// agcUnderRangeHighInterval
		30, 		// apdHighThresh
		49,			// apdLowGainModeHighThresh
		10,			// apdLowThresh
		19,			// apdLowGainModeLowThresh
		6,			// apdUpperThreshPeakExceededCnt
		3,			// apdLowerThreshPeakExceededCnt
		2, 			// apdGainStepAttack
		2,			// apdGainStepRecovery
		0,			// enableHb2Overload
		1,			// hb2OverloadDurationCnt
		1,			// hb2OverloadThreshCnt
		181,		// hb2HighThresh
		45,			// hb2UnderRangeLowThresh
		90,			// hb2UnderRangeMidThresh
		128,		// hb2UnderRangeHighThresh
		6,			// hb2UpperThreshPeakExceededCnt
		3,			// hb2LowerThreshPeakExceededCnt
		2,			// hb2GainStepHighRecovery
		4,			// hb2GainStepLowRecovery
		8,			// hb2GainStepMidRecovery
		4,			// hb2GainStepAttack
		1,			// hb2OverloadPowerMode
		0,			// hb2OvrgSel
		3,			// hb2ThreshConfig
		3,			// hb2UnderRangeLowThreshExceededCnt
		3			// hb2UnderRangeMidThreshExceededCnt
	}
};

